As it is well known in this specific technical field, during the last ten years, the use of FPGA architectures has been a valid solution for a multiplicity of tasks.
In the meanwhile, the applications realized by such FPGA architectures have become so much more and more complex that they comprise many different algorithms which are implemented by a same FPGA architecture in different moments.
To increase the possibilities of using FPGA architectures, the possibility of run-time reconfiguration, i.e. during the operation of the architecture itself, has been introduced, in particular by reprogramming the gate arrays comprised in the architecture.
A typical configuration of an FPGA architecture is schematically shown in FIG. 1 and globally indicated with 1. The FPGA architecture 1 essentially comprises a plurality of programmable logic elements 2 arranged in a matrix-like configuration, commonly indicated as gate arrays, each of such programmable logic elements 2 being connected, by means of a plurality of local connections 3, to an interconnection network 4, in turn comprising a plurality of horizontal interconnection lines 4a and vertical interconnection lines 4b. 
As shown in FIG. 1, each programmable logic element 2 of the gate array essentially comprises a look-up table 5 having a plurality of inputs and being connected to an output through a multiplexer 6 having in turn an input connected to a memory element 7.
In particular, the interconnection network 4 allows to reconfigure the FPGA architecture 1, changing the operation thereof.
FIG. 2 schematically shows a detail of the FPGA architecture 1, in particular a programmable logic element 2 and its connections to the interconnection network 4.
The programmable logic element 2 is connected to a horizontal connection block 8a and to a vertical connection block 8b in turn connected to a switch matrix or switch block 10. The connection blocks 8a and 8b as well as the switch block 10 comprise a plurality of connection lines 9.
As shown in FIG. 2, a SRAM memory cell 11 is connected to each intersection of the connection lines 9, such cell driving a MOS transistor 12 to program the interconnections of the programmable logic element 2 inside the gate matrix of the FPGA architecture 1.
In FPGA architectures of this type, the area occupation and the propagation delay are essentially linked to the connection blocks and to the programmable switch blocks. Moreover, such switch blocks are extremely complex.
In particular, a complete reconfiguration of an FPGA architecture as described typically requires several hundreds of clock cycles and thus causes delays which considerably affect the overall performances of the system the FPGA architecture is part of.
To limit the delays due to the reconfiguration time of the FPGA architectures, multi-context FPGA architectures have been thus recently proposed able to store different configurations inside the gate array of the architecture itself, allowing context switching in a very short time. In such architectures, different contexts coexist of which only one is active. The switching from a context to another causes the change of the FPGA architecture operation.
An FPGA architecture 30 of the multi-context type is schematically shown in FIG. 3. In particular, the multi-context FPGA architecture 30 comprises a plurality of configurations, in the example shown equal to four configurations indicated with 30a-30d, ready to be used. Only one of such configurations, in particular a first configuration 30a, is active.
The passage from a pre-stored configuration to another thus occurs in very short periods of time.
This advantage is not however without costs: each SRAM cell used to store configuration bits in a multi-context FPGA architecture is typically replicated by a number equal to that of the stored contexts, as schematically shown in FIG. 4, where it is highlighted that a plurality of SRAM cells 11a-11d are comprised in each switch block 10.
A multi-context FPGA architecture is described for example in the article “A Time-Multiplexed FPGA” to S. Trimberger et al. (Xilinx Inc.).
In essence, by using a multi-context FPGA architecture a great increase of the area occupation of the architecture itself occurs, which causes an increase of the length of the interconnection lines which in turn affects the delays and the power consumption, in a more and more significant way with the reduction of the integration technology scale.
Since the increase of the area occupation and of the delays is essentially due to the high number of interconnections which realize the programmability of the FPGA architecture, the efforts in the field have been addressed to their configuration.
Thus, the interconnections represent a more and more important key requirement for re-programmable architectures, where devices such as pass transistors, three-state buffers or multiplexers, increase the area occupation and the capacitive load on the wires or connectors, affecting the overall performance.
As already seen, the switch blocks 10 are also of particular importance, being responsible for the connection between the horizontal interconnection lines 4a and the vertical interconnection lines 4b. It is possible to state that the FPGA architecture reconfigurability and a significant part of the delays due to the interconnections are related to such switch blocks 10.
It is known to realize such switch blocks 10 by means of a configuration with six pass-transistors, described for example in the U.S. Pat. No. 4,870,302 issued on Sep. 26, 1989 to Xilinx, Inc. and schematically shown in FIG. 5A.
In particular, once four directions are identified with N, E, S, W, the switch block 10A comprises in fact six pass transistors 13 connected to respective pairs of directions, in particular to the directions N-E, E-S, S-W, W-N, N-S and W-E. Each pass-transistor 13 has a control terminal connected to a respective SRAM cell 11.
Although advantageous from a flexibility and small area occupation point of view, such a switch block 10A architecture has a high interconnection delay due to the serial connections of the pass-transistors comprised therein.
Such delay is unacceptable when the technological integration scale of the devices comprising the FPGA architectures at issue, wherein the delay time portion due to the interconnection mechanism is more and more preponderant, increases.
For such reason, solutions for switch blocks have been recently proposed wherein the technologies linked to the pass-transistors and to the three-state buffers are associated, as described for example in the U.S. Pat. No. 4,835,418 issued on May 30, 1989 to Xilinx Inc. and schematically shown in FIG. 5B.
In FIG. 5B, a switch block 10B is particularly shown comprising six bi-directional three-state buffers 14, each comprising a pair of buffers driven by respective SRAM cells 11a, 11b and connected to each other in a crossed way. As in the switch block 10A of FIG. 5A, the bi-directional three-state buffers 14 of the switch block 10B are also connected to respective pairs of directions, in particular to the directions N-E, E-S, S-W, W-N, N-S and W-E.
Such a solution, although reducing the propagation delay thanks to the absence of pass-transistors in series with each other, has the drawback of needing a large integration area due to the dimensions of the buffers and to the number of SRAM cells, doubled with respect to the switch block 10A.
Other circuit solutions are known to realize switch blocks by means of bi-directional three-state buffers as described in the U.S. Pat. No. 5,600,264 issued on Feb. 4, 1997 and U.S. Pat. No. 5,760,604 issued on Jun. 2, 1998, both to Xilinx, Inc.
In any case, the circuit solutions proposed by the prior art comprise switch blocks with three-state buffers requiring two configuration bits to determine both the on/off state and the signal direction, and are thus inefficient in terms of area occupation, which is linked to the number of SRAM cells in the device. Known solutions are thus essentially dedicated to reducing the number of three-state buffers and of SRAM cells comprised in the switch blocks.
In this perspective, the solution described in U.S. Pat. No. 5,376,844 issued on Dec. 27, 1994 to Altera Corp. has been developed, wherein multiplexing blocks are used to reduce the number of SRAM cells necessary to realize the programming of the interconnections in an FPGA architecture.
Although advantageous in several aspects, such a known solution also has problems linked to the area occupation, in particular in the case of FPGA architectures of the multi-context type, wherein SRAM memory cells are typically multiplied by the number of the configurations pre-stored in the FPGA architecture itself.